# -*- mode:python -*-

# Copyright (c) 2015 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder.  You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Copyright (c) 2006 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Import('*')

SimObject('Ethernet.py', sim_objects=[
    'EtherLink', 'DistEtherLink', 'EtherBus', 'EtherSwitch', 'EtherTapBase',
    'EtherTapStub', 'EtherDump', 'EtherDevice', 'IGbE', 'EtherDevBase',
    'NSGigE', 'Sinic'] +
    (['EtherTap'] if env['CONF']['HAVE_TUNTAP'] else []))

# Basic Ethernet infrastructure
Source('etherbus.cc')
Source('etherswitch.cc')
Source('etherdevice.cc')
Source('etherdump.cc')
Source('etherint.cc')
Source('etherlink.cc')
Source('etherpkt.cc')
Source('ethertap.cc')

Source('pktfifo.cc')

DebugFlag('Ethernet')
DebugFlag('EthernetCksum')
DebugFlag('EthernetDMA')
DebugFlag('EthernetData')
DebugFlag('EthernetDesc')
DebugFlag('EthernetEEPROM')
DebugFlag('EthernetIntr')
DebugFlag('EthernetPIO')
DebugFlag('EthernetSM')

# Dist gem5
Source('dist_iface.cc')
Source('dist_etherlink.cc')
Source('tcp_iface.cc')

DebugFlag('DistEthernet')
DebugFlag('DistEthernetPkt')
DebugFlag('DistEthernetCmd')

# Ethernet controllers
Source('i8254xGBe.cc')
Source('ns_gige.cc')
Source('sinic.cc')



CompoundFlag('EthernetAll', [ 'Ethernet', 'EthernetPIO', 'EthernetDMA',
    'EthernetData' , 'EthernetDesc', 'EthernetIntr', 'EthernetSM',
    'EthernetCksum', 'EthernetEEPROM' ])

CompoundFlag('EthernetNoData', [ 'Ethernet', 'EthernetPIO', 'EthernetDesc',
    'EthernetIntr', 'EthernetSM', 'EthernetCksum' ])
